ELEC3720 - Electrical Engineering - Programmable logic design - Assessment Answer

December 13, 2018
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Electrical Engineering Assignment

Case Scenario/ Task

In this assignment you will design the instruction set architecture of a simple microprocessor.

  • Assignemt 2 is a group assignment. Each group should consist of two students. You are welcome to form your own group. It is fine if you prefer to work alone.
  • This assignment is due on the Friday of week-9, at 17:00 hrs. Please submit your report via blackboard. Go to the ‘Assessments’ folder and then follow the ‘Assignment 2.1 submission portal’ link. In addition, each group is required to submit the hardcopy of the report which should include the following:

– The assessment item cover sheet; – Description of your design.

The report should be dropped in the ELEC3720 drop-box located in the ground floor of the EA building before the deadline.

  • The project report must at least clearly describe the instruction set architecture, and how that architecture is implemented on hardware.
  • You will be asked to demonstrate the hardware implementation of your design in Assignments 2.2 and 2.3.
  • Note that you are may be required to answer some questions on your design some time during the scheduled lab hours on week 10.

Problem.

  1. Design the instruction set architecture of a single cycle processor with 18 bit wide instructions, and data-word width of your choice. Show the hardware implementation details of the processor. In particular, provide the

  • Instruction set along with the binary codes
  • Instruction encoding/decoding logic
  • Discuss various tradeoffs made in your design to optimize the following:

– Instruction coverage – Dataword width, – Number of registers, – Memory adressing scheme (byte or word addressable, base/offset based addressing) – Memory address and offset range – Jump offset range – Branch offset range

1

  • Show the data path needed to implement your design

• Discuss the the control signals and their logic The complexity and the effort needed depends significantly on the data word width of the processor. This the marks automatically depend on the data word width. You should aim for at least 16 bit wide data words.

The utility and efficiency of a processor depends significantly on the number of registers. Hence one prefers to have as many resgisters as possible. However, having more than 32 registers typically slows down a processor due to the increase in the address decoding time.

Similarly, it is desirable to have large memory offset range, jump offset range and branch offset range.Aim to implement as many instructions from the standard MIPS instruction set as possible, and justify why it is not required/possible to implement more.

Marking criterion.

The mark is allocated as follows:

  1. Description of the instruction set (5)
  2. Instruction encoding/decoding logic (5)
  3. Rationale behind the design and associated design trade-offs (12)
  4. Instruction coverage (28)

  • ALU instructions with register operands (4)
  • Multiplication/Division instructions with register operands (4)
  • Shift instructions with register operands (4)
  • ALU instructions involving constant operands (4)
  • Branch instructions (4)
  • Jump instructions (4)
  • Memory read and write instructions (4)

  1. Description of datapath, control signals and control signals’ logic (3+3+4 = 10)

 

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Solution: Electrical Engineering

The Central Processor - Control and Dataflow:

we sketched out an ALU in perspective of building squares, for instance, multiplexers for selecting an operation to convey ALU yield, pass on look ahead adders to diminish the multifaceted nature and (for all intents and purposes) the fundamental path length of calculating operations, and parts, for instance, coprocessors to perform excessive operations, for instance, skimming point calculating. We similarly illustrated that PC calculating encounters botches on account of restricted precision, nonappearance of associativity, and limitations of traditions.

Review:

In past sections, we discussed PC relationship at the little scale designing level, processor affiliation and also method of reasoning circuits including timing rationalities and progressive circuits, for case, snares. In Fig, the consistent relationship of a current processor is appeared. Observe that the Central Processing Unit memory subsystem, and Input/output system are related by address, data, and control transports. The way that these are similar transports is implied by the slice through each line that hints a vehicle.

It is helpful to advance talk about the associated parts in Fig: Processor is the dynamic part of the PC, which does all the work of data control and basic leadership.  Data way is that equipment that plays out all the required operations atoccurrence, ALU or registers or and inner transports.  Control is the equipment that advises the information way what to do, as far as exchanging, operation excellent, information progress between ALU parts, and so forth. The processor spoke to by the shaded piece in Fig is composed as appeared in Watch that the ALU performs Input and output on information put away in the enlist document and the control Unit sends  control signals  in combination with the register .

In MIPS and ISA decides numerous parts of the processor usage. For illustration, execution procedures and objectives influence clock rate and CPI. Theusage requirements cause constraintsof the parts in Fig is adjusted all through plan procedure.

Such use concerns are reflected in the usage of method of reasoning parts and timing methodology. Case in point, with combination parts, for instance, adders, multiplexers, or shifters, harvests depend just on current data sources. In any case back to back parts, for instance, memory and registers contain state information and what's more, their yield along these lines depends on upon their data sources furthermore on the set away state. The clock chooses the demand of events inside an entryway, and portrays when signs can be changed over to data to be examined or stayed in contact with processor fragments for explanations behind study, the going with chart of timing is existing.

Here a banner that is detained at method of reasoning high regard is said to be expressed. In Section, we analyzed how edge-enacted timing can reinforce a correct state proceed onward the element clock beat edge. We in like manner investigated the SR Latch in perspective of nor method of reasoning, and illustrated how this could be changed over to a coordinated SR snare. From this, planned D Latch and the D flip-tumble were resolved. In particular, the D flip-flop has a falling-edge trigger, what's more, its yield is at initially sold out.

Reg file:

The RF is an equipment gadget that has two perused ports and one compose port. The RF and the Arithmetic logic unittogether incorporate the two segments required to figure. Mips  R - mastermind Arithmetic logic unit headings. The RF is incorporated a game plan of registers that can be examined or made by providing a select number to be gotten to, as well as a make endorsement bit. A diagramof RF is shown in Fig.

Data Path:

The data path is the "cerebrum" of a processor, meanwhile it actualizes the bring unravel execute cycle. general train for data path outline is to

  • Decide the guideline classes and configurations in the ISA,
  • Outlinedata path segments and interconnections for every direction lesson or configuration.
  • Make the data path sections outlined in Step two to yield a composite data path. Straightforward data path parts incorporate memory PC.
  • Utilization of the data path of I-and J-outline rules needs memory in 2 parts and a sign extend in Fig. The data memory stores Arithmetic logic unit results and operands, counting rules, and has two allowing sources of info that can't both be progressive meanwhile. The data memory recognizes an address and either recognizes data or yields data at the demonstrated address. The sign extend ads 16 driving digits to bits  word with most gigantic piece b, to thing a 32-bit word. In precise the additional 16 digits have the same regard as in B, in this way realizing sign enlargement in twos supplement representation.
  • Set-up Data path:Execution of the data path for R-arrange guidelines is genuinely clear - the Enlist document and the Arithmetic logic unitare is required. The Arithmetic logic unit acknowledges its contribution from the Data Read ports of the enlist record, and the enlist document is composed to by the Arithmetic logic unit result yield of the Arithmetic logic unit, in mix with Rewrite flag
  • The load/store data path is exemplified in Fig, and achieves the following activities in the command given

    • Register take input from the register file  to instrument the instruction or

    Data oraddress fetch step of the fetch decode execute cycle.

    • Control decodes the base add and offset, bonding them to crop the actual mem address. This step usages the sign extender and Arithmetic logic unit.
    • Read or Write from the Memory takes data or and apparatuses the first part of the execute step of the fetch or decode or execute cycle.
    • When we write in register file we are putting data in the memory, applying the another part of the perform step of the fetch or decode or execute cycle
    • Load or Store Instruction.Execution of a load or store instruction using the data path developed in Section shows includes the following steps:

      1. instruction are fetch from memory and increase pc.
      2. value of register is read from register file contain.
      3. Arithmetic logic unitadds the base address from register  to the sign-extended lower 16- bits of the instruction.
      4. Result from arithmetic logic unit is practical as an address to the data memory
      5. Data saved from the memory unit is record in the register file, where the register index

      Branch Instruction.

      Execution of a branch instruction using the data path developed includes the following steps:

      1. Fetch instruction from instruction memory and increment PC
      2. Read registers from given the register file. The adder sums PC plus 4 plus sign lengthy lower 16 bits of offset shifted left by two bits, thereby producing the BTA.
      3. Arithmetic logic unit minus fillings of T1 minus innards of T2. The Zero output of the Arithmetic logic unit Directs which result to write as the new PC.

      Final Control Design. 

      Now we have strong-minded the movements that the data path must do to calculate the three types of MIPS orders that we can use the

      Info in to describe the control logic truth table

    • The resulting augmented data path is shown
    • LimitsinSingleCycle Data pathThe single-cycle data path is not used in current processors, since it is extravagant. The basic way is five parts for the mound direction. The process period is incomplete by the relaxing time ts of these sections. For a circuit with no input circles,  TC greater than 5ts. Almost speaking, TC equal to 5-kts, with extensive proportion reliable k, because of input circles, suspended settling because of circuit appeal, and so on. The outcome is the Load that guideline takes five units of time, while the Store and R-design directions take four units of time. The many sorts of schemes that the data path is future to execute run speedier, challenging three units of time. The  issue of exhausting growth, minus, and connection processes to oblige load and store drives one to inquire as to whether frequent cycles of a manyswifterclock could be utilized for every part of the bring unravel execute cycle. By and by, this system is applied in central processing unit plan and execution, as talked about multi cycle data path outline.

       

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